1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly, to an improved fabrication method
2. Discussion of the Related Art
Demand for information displays is growing as the demand for portable (mobile) information devices increases. In some devices thin flat panel displays (FPD) are used. These FPDs have Liquid Crystal Displays (LCD) that use an optical anisotropy of a liquid crystal. The medium exhibits excellent resolution, color, and picture quality.
Some LCDs have multiple substrates in which a liquid crystal layer is formed between a color filter substrate and an array substrate. Thin film transistors (TFTs) are used as switching elements in these displays. The LCD in FIG. 1 includes a color filter substrate 5, an array substrate 10, and a liquid crystal layer 30. The color filter substrate 5 includes color filters (C) that have sub-color filters 7 that generate red, green, and blue colors. Black matrixes 6 separate the sub-color filters 7 and block light transmission to the liquid crystal layer 30. A transparent common electrode 8 applies a voltage to the liquid crystal layer 30. The array substrate 10 of FIG. 1 includes a plurality of gate lines 16 and data lines 17 that form a plurality of pixel regions (P). TFTs are formed at each crossing of the gate lines 16 and data lines 17, and pixel electrodes 18 are formed on each pixel region (P).
The color filer substrate 5 and the array substrate 10 are attached in adjacent positions using a sealant. Two substrates 5 and 10 are attached through an attachment key.
The LCD shown in FIG. 1 is a twisted nematic (TN) type LCD in which nematic liquid crystal molecules are driven in a perpendicular direction relative to the substrates. When a voltage is applied to the liquid crystal display panel, liquid crystal molecules that have been aligned horizontally to the substrates are aligned in a vertical direction.
In FIG. 2, the N number of gate lines and M number of data lines in a plane switch (IPS) mode LCD cross each other to from M×N number of pixels on an array substrate. A gate line 16 and a data line 17 positioned vertically and horizontally form a pixel region on a transparent glass substrate 10. A TFT is formed at the crossing of the gate line 16 and the data line 17.
The TFT includes a gate electrode 21 connected to the gate line 16. A source electrode 22 is connected to the data line 17, and a drain electrode 23 is connected to a pixel electrode 18 through a pixel electrode line 181. The TFT includes a first insulation film for insulating the gate electrode 21 and the source and drain electrodes 22 and 23. An active pattern forms a conductive channel between the source electrode 22 and the drain electrode 23.
In the pixel region, a plurality of common electrodes 8 and a plurality of pixel electrodes 18 are alternately disposed in a direction parallel to the data line 17. The pixel electrodes 18 are connected with the pixel electrode line 181 through a first contact hole 40a. The pixel electrodes 18 are electrically connected with the drain electrode 23 and the common electrodes 8 are electrically connected to a common electrode line 81 in parallel with the gate line 16 through a second contact hole 40b. 
In FIG. 3A, a gate electrode 21, a gate line, and a common line are formed on a substrate 10 through a photolithography process (a first making process). In FIG. 3B, a first insulation film 15a, an amorphous silicon thin film, and an n+ amorphous silicon thin film are sequentially deposited on the entire surface of the substrate 10 with the gate electrode 21. The gate line and the common line are then formed, and the amorphous silicon thin film and the n+ amorphous silicon thin film are selectively patterned using photolithography (a second masking process) to form an active pattern 24. At this stage, the n+amorphous silicon thin film pattern 25 which has been patterned in the same form as the active pattern 24 is formed.
Thereafter, as shown in FIG. 3C, a conductive metal is deposited on the entire surface of the substrate 10 and then selectively patterned through photolithography (a third masking process). The photolithography forms a source electrode 22 and a drain electrode 23 at an upper portion of the active pattern 24. At this stage, a certain portion of the n+ amorphous silicon thin film pattern formed on the active pattern 24 is removed through the third masking process to form an ohmic contact layer 25n. 
In FIG. 3c, a portion of the source electrode 22 extends in one direction to form the data line 17, and a portion of the drain electrodes 23 extends to the pixel region to form the pixel electrode line 181. Next, in FIG. 3D, a second insulation film 15b is deposited on the entire surface of the substrate 10 with the source electrode 22 and the drain electrode 23 formed. A portion of the second insulation film 15b is removed through photolithography (a fourth masking process) to form a contact hole 40a exposing a portion of the pixel electrode line 181. At this stage, another portion of the second insulation film 15b is removed through the fourth masking process to form a second contact hole exposing a portion of the common line.
Finally, as shown in FIG. 3E, a transparent conductive metal material is deposited on the entire surface of the substrate 10 and then selectively patterned using photolithography (a fifth making process) to form pixel electrodes 18 that are electrically connected with the pixel electrode line 181 and the common electrodes 8 that are electrically connected with the common line in FIG. 2.
When fabricating some array substrates that include TFTs, at least five photolithography processes are performed to pattern the gate electrode, the active pattern, the source and drain electrodes, the contact holes, and the pixel electrodes. Successive photolithography processes may degrade production yields, decrease reliability, and increase the likelihood of a defective TFT. Because the masks used to form pattern can be very expensive, as more masks are applied, the fabrication cost of the LCD increases. Therefore, there is a need for a cost efficient fabrication process that may increase production yields, improve reliability, and decrease production defects.